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Pages

About me

Posts

Future Blog Post

less than 1 minute read

Published:

This post will show up by default. To disable scheduling of future posts, edit config.yml and set future: false.

Blog Post number 4

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 3

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 2

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 1

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

portfolio

publications

ReSCIM: Variation-Resilient High Weight-Loading Bandwidth In-Memory Computation Based on Fine-Grained Hybrid Integration of Multi-Level ReRAM and SRAM Cells

Published in ICCAD, 2024

This paper presents a high weight-loading bandwidth hybrid ReRAM and SRAM cell for Computing-in-Memory.

Recommended citation: Xiaomeng Wang*, Jingyu He*, Kunming Shao, et al. ReSCIM: Variation-Resilient High Weight-Loading Bandwidth In-Memory Computation Based on Fine-Grained Hybrid Integration of Multi-Level ReRAM and SRAM Cells. In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1–9. IEEE, 2024. https://doi.org/10.1145/3676536.3676751

SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis

Published in DATE, 2025

This paper presents a performance-aware DCIM compiler with multi-spec-oriented subcircuit synthesis.

Recommended citation: Kunming Shao*, Fengshi Tian*, Xiaomeng Wang, et al. SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis. In 2025 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–6. IEEE, 2025. https://arxiv.org/pdf/2411.16806

E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-model In-Memory Inference/Training for Personalized Medical Wearables

Published in CICC, 2025

This paper presents an event-driven adaptive neural SoC with signal-dynamics-aware feature clustering and multi-model in-memory inference/training for personalized medical wearables.

Recommended citation: Fengshi Tian*, Jinbo Chen*, Kunming Shao*, et al. E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-model In-Memory Inference/Training for Personalized Medical Wearables. In 2024 IEEE Custom Integrated Circuits Conference (CICC), pages 1–2. IEEE, 2025. To be released later

A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination

Published in ISCAS, 2025

This paper presents a reconfigurable DNN accelerator for continuous activation/weight precisions with efficient weight combination.

Recommended citation: Liang Zhao*, Kunming Shao*, Fengshi Tian, et al. A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination. In 2025 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–6. IEEE, 2025. https://arxiv.org/abs/2502.00687

talks

teaching

Analog Electronics

Undergraduate course, SCUT, 2022

This is the course for Chinese Postgraduate Entrance Examination. I was the lecturer of this unofficial course, and we used Neamen’s Microelectronics: Circuit Analysis And Design, Fourth Edition