Published in BioCAS, 2025
This paper presents a efficient vector retrieval accelerator for RAG leveraging hierarchical approximate retrieval.
Recommended citation: See google scholar https://arxiv.org/html/2510.27107v1
Published in ISLPED, 2025
This paper presents a efficient vector retrieval accelerator for RAG leveraging digital in-reram computing.
Recommended citation: K. Shao, Z. Liao, J. Yu, L. Zhao, Q. Li, X. Huang, J. He, F. Tian, Y. Zou, X. Wang, T. K.-T. Cheng, and C.-Y. Tsui, “Dirc-rag: Accelerating edge rag with robust high-density and high-loading-bandwidth digital inreram computation,” in 2025 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2025, pp. 1–7. https://arxiv.org/abs/2510.25278
Published in ISCAS, 2025
This paper presents a reconfigurable DNN accelerator for continuous activation/weight precisions with efficient weight combination.
Recommended citation: Liang Zhao*, Kunming Shao*, Fengshi Tian, et al. A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination. In 2025 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–6. IEEE, 2025. https://arxiv.org/abs/2502.00687
Published in CICC, 2025
This paper presents an event-driven adaptive neural SoC with signal-dynamics-aware feature clustering and multi-model in-memory inference/training for personalized medical wearables.
Recommended citation: Fengshi Tian*, Jinbo Chen*, Kunming Shao*, et al. E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-model In-Memory Inference/Training for Personalized Medical Wearables. In 2024 IEEE Custom Integrated Circuits Conference (CICC), pages 1–2. IEEE, 2025. To be released later
Published in DATE, 2025
This paper presents a performance-aware DCIM compiler with multi-spec-oriented subcircuit synthesis.
Recommended citation: Kunming Shao*, Fengshi Tian*, Xiaomeng Wang, et al. SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis. In 2025 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–6. IEEE, 2025. https://arxiv.org/pdf/2411.16806
Published in ICCAD, 2024
This paper presents a high weight-loading bandwidth hybrid ReRAM and SRAM cell for Computing-in-Memory.
Recommended citation: Xiaomeng Wang*, Jingyu He*, Kunming Shao, et al. ReSCIM: Variation-Resilient High Weight-Loading Bandwidth In-Memory Computation Based on Fine-Grained Hybrid Integration of Multi-Level ReRAM and SRAM Cells. In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1–9. IEEE, 2024. https://doi.org/10.1145/3676536.3676751
Published in DAC, 2023
This paper presents the first spec-to-layout circuit compiler for digital computing-in-memory macros.
Recommended citation: Jia Chen, Fengbin Tu, Kunming Shao, et al. AutoDCIM: An Automated Digital CIM Compiler. In 2023 60th ACM/IEEE Design Automation Conference (DAC), pages 1–6. IEEE, 2023. https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10247976